At 80°C, most modern CPUs are operating within a "warm but safe" zone under heavy load. However, this is often the temperature where thermal protection mechanisms begin to wake up to prevent damage.
The image above illustrates the CPU thermal detection circuit, which can be categorized into the following key sections:
1.VL Signal: This is the primary power rail originating from the Standby Power Supply section. It provides a constant 5V output to power the PU3 IC, the PH1 thermistor, and the inverting input (Pin 2) of the PU3 operational amplifier (Op-Amp).
2.PU3 Op-Amp (LM393): This IC functions as a voltage comparator, comparing the input voltages at Pin 3 (Non-inverting) and Pin 2 (Inverting). The comparison result is toggled at the output (Pin 1), where a HIGH state indicates the presence of voltage and a LOW state indicates no voltage.
3.PH1 NTC Thermistor: This is a Negative Temperature Coefficient (NTC) thermistor with a nominal resistance of 100KΞ©. As the ambient temperature rises, its internal resistance decreases, subsequently causing the voltage drop across the component to decrease.
4.MAINPWON Signal: This serves as the connection point to the 3.3V/5V Standby Power Supply. Under normal operating conditions, this signal must remain in a Logic High state, with a measured voltage of 5V.
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The following figure illustrates the approximate voltage measurements from an actual motherboard. As shown, the VL voltage is 5V, supplied by the primary standby power rail. The critical points are pins 2 and 3 of the Op-Amp IC (PU3).
The voltage at pin 2 is derived from the VL source passing through a voltage divider network consisting of resistors PR27 and PR29. Since both resistors have identical resistance values, the voltage is divided equally, resulting in approximately 2.5V across PR29.
In contrast, the voltage at pin 3 remains very low, approximately 0.5V, under normal CPU operating temperatures. This is because PH1 (Thermistor) maintains a high resistance, limiting current flow and resulting in a minimal voltage drop across PR26. Consequently, the input voltage at pin 3 is also minimal.
When the voltage at pin 3 (Non-inverting input) is lower than the voltage at pin 2 (Inverting input), the output at pin 1 of PU3 triggers a LOW state (approximately 0V or Ground). This keeps the MOSFET PQ6 in an 'OFF' state, creating high resistance between the Source and Drain. As a result, the 5V MAINPWON signal cannot pass through the MOSFET
